(1) Field of the Invention
The present invention relates to a data input-output device, and especially relates to a data input-output device that outputs input data after performing specific operations on the data, where data is input and output at a respectively predetermined transmission rates.
(2) Description of the Prior Art
A data input-output device needs to be provided in a computer or audiovisual equipment in order to use digital data stored on an optical disc or a magnetic disk.
The data input-output device reads data stored on an optical disc and manipulates or corrects the data as necessary, and transmits the data to a computer after converting the format of the data so that the data may be used by the computer.
(Optical disc Reader)
The following is the explanation of the above-mentioned example of a data input-output device, that is, a conventional optical disc reader in accordance with FIGS. 1 to 5.
FIG. 1 shows the overall construction of a conventional optical disc reader.
Optical disc reader 1000 roads data recorded on optical disc 1010, and transmits the data to host computer 1070 after correcting any errors in the fetched data. Optical disc reader includes pickup 1020, amplifier 1030, front end processor 1040, optical disc control unit 1100, rotation motor 1050, servo controller 1060, and system control unit 1200.
System control unit 1200 is a microprocessor that interprets a command to obtain data, the command having been received from host computer 1070 via optical disc control unit 1100, and executes the command by controlling servo controller 1060 and optical disc control unit 1100.
Rotation motor 1050 rotates optical disc 1010. On receiving the instructions from system control unit 1200, servo controller 1060 controls the rotation of rotation motor 1050 and the lens position in pickup 1020 according to the information from front end processor 1040.
Pickup 1020 reads data recorded on optical disc 1010 by directing a laser beam at the optical disc and transforming reflected light into electrical signals. Amplifier 1030 amplifies the signals output by pickup 1020 and outputs the signals to front end processor 1040.
Front end processor 1040 performs feedback control of servo controller 1060, rotation motor 1050, and pickup 1020 according to the input signals to output stable signals to optical disc control unit 1100. Front end processor 1040, which includes an equalizer, an AGC (automatic gain control), and a PLL (phase-locked loop), outputs signals, that is, modulated data, to optical disc control unit 1100.
Optical disc control unit 1100 informs the system control unit 1200 of a command to obtain data that was issued by host computer 1070. Under the control of system control unit 1200, optical disc control unit 1100 demodulates the signals input from front end processor 1040 to obtain the requested data, and transmits the data to host computer 1070 after performing an error correction process on it.
The bold lines in FIG. 1 show the data flow from optical disc 1010 to host computer 1070. The data recorded on optical disc 1010 is transmitted to host computer 1070 via pickup 1020, amplifier 1030, front end processor 1040, and optical disc control unit 1100.
The following is a detailed explanation of optical disc control unit 1100 in a conventional optical disc reader in accordance with FIG. 2.
FIG. 2 shows the construction of optical disc control unit 1100 in a conventional optical disc reader.
Optical disc control unit 1100 includes first memory 1110, second memory 1120, third memory 1130, disk interface unit 1140, error correction unit 1150, host interface unit 1160, first transfer unit 1170, and second transfer unit 1180.
The bold lines in FIG. 2 show the data flow from front end processor 1040 to host computer 1070.
Disk interface unit 1140 demodulates the signals input from front end processor 1040 to obtain the requested data, and stores the data in first memory 1110.
Error correction unit 1150 performs an error correction process on a predetermined number of bytes of data that disk interface unit 1140 stores in first memory 1110, and corrects the data when necessary. The above-mentioned predetermined number of bytes of data is the amount of data included in one block of data, that is, the processing unit on which an error correction process is performed. Hereinafter, this predetermined number of bytes of data will be called a block of data. The error correction process performed by error correction unit 1150 will be explained later in detail.
First transfer unit 1170 transfers data which has been subjected to the error correction process by error correction unit 1150 and stored in first memory 1110 to second memory 1120.
First memory 1110 has a capacity of one megabit and includes three areas which each can store one block of data.
Disk interface 1140, error correction unit 1150, and first transfer unit 1170 operate independently. Each of the three areas is accessed by one of disk interface unit 1140, error correction unit 1150, and first transfer unit 1170 simultaneously in a fixed interval. The area accessed by disk interface unit 1140 is accessed by error correction unit 1150 in the next interval. The area accessed by error correction unit 1150 is accessed by first transfer unit 1170 in the next interval. The area accessed by first transfer unit 1170 is accessed by disk interface unit 1140 in the next interval.
In terms of memory access, this means that first memory 1110, as a whole, is simultaneously accessed by three different units, disk interface unit 1140, error correction unit 1150, and first transfer unit 1170 and so needs to be constructed to allow such simultaneous access.
In terms of each block this means that disk interface unit 1140 first stores one block of data in first memory 1110, secondly error correction unit 1150 performs an error correction process on the data, and thirdly first transfer unit 1170 transfers the data to second memory 1120.
Second memory 1120 stores the data transferred from first transfer unit 1170, with the data then being transferred to third memory by second transfer unit 1180.
Third memory 1130 is a four megabit memory which stores up to 15 blocks or data. Third memory 1130 stores the data transferred from an optical disc via first memory 1110 and second memory 1170.
Host interface unit 1160 transfers the data transfer command from host computer 1070 to system control unit 1200, and transmits the data stored in third memory 1130 to host computer 1070 on the instructions from system control unit 1200.
System control unit 1200 manages the data stored in third memory 1130, and when host computer 1070 requests the transmission of the data not stored in third memory 1130, drives rotation motor 1040 via servo controller 1060 to transmit to host computer 1070 the data transferred to third memory 1130 by controlling host interface unit 1160.
The components of conventional optical disc control unit 1100 can be broadly classified into two parts: one part, the core unit of which is first memory 1110, reads data and performs the error correction process; and the other part, the core unit of which is third memory 1130, transmits data to host computer 1070. Second memory 1120 connects these two parts as a FIFO (first-in first-out) buffer.
Data is input from front end processor 1040 to disk interface unit 1140 at low speed. On the other hand, data needs to be output from host interface unit 1160 to host computer 1070 at high speed in order not to delay the process performed in host computer 1070. Therefore, conventional optical disc control unit 1100 has a construction where the low speed processing part and the high speed processing part are connected with a buffer.
(Error Correction Unit)
The following is the detailed explanation of error correction unit 1150 included in optical disc control unit 1100 in conventional optical disc reader 1000 mentioned above.
First of all, the error correction process performed by error correction unit 1150 is explained.
The recording density of a recording medium, such as an optical disc which records digital data, is so high that even a tiny crack in the medium, fine dirt, and fine dust can easily cause data errors. Therefore, a reader such as an optical disc reader may not always read data correctly.
In order to read data correctly, the error correction process is performed. An error-correcting code is added to a piece of data when the data is recorded on a recording medium, and the reader of the recording medium detects and corrects erroneous data using the error-correcting code. A Reed-Solomon code is an error-correcting code that is very effective at correcting erroneous data.
FIG. 3 shows an example of an error-correcting code. This example is a product code which is the most fundamental code that can be produced by combining two codes.
In C1 direction k1 bytes of parity data is added to n1xn2 bytes of information data 1311, and k2 bytes of parity data is added in C2 direction. k2 bytes of parity data is added to C1 parity data in C2 direction.
Therefore, k1xn2 bytes of parity data 1312, n1xk2 bytes of parity data 1313, and k1xk2 bytes of parity data 1314 is added to information data 1311. Consequently, (n1+k1).times.(n2+k2) bytes of data forms one block of data, that is, the processing unit on which an error correction process is performed.
The error correction process is performed on the product code shown in FIG. 3 in the following manner. Firstly, an error correction process is performed on n1 bytes of information data in each row from the first row to the (n2+k2)th row using the k1bytes of parity data in C1 direction. This will correct errors included in the information data to some extent. Secondly, an error correction process is performed on n2bytes of information data in each column from the first column to the (n1+k1)th column using the parity data in C2 direction in order to increase the accuracy of the information data. Thirdly, additional error correction calculations performed using the parity data in C1 direction further increase the accuracy of the information data.
The error correction process using the parity data in C1 direction on the first row of the information data is performed in the following process.
(1) A syndrome is calculated from one row of information data and parity data. When the value of a multidimensional syndrome is "0", that is, the value of each component of the syndrome is "0", no error is included in the row of information data.
(2) An error position polynomial and an error value polynomial are calculated based on the syndrome by a method such as Euclid's algorithm.
(3) The root of the error position polynomial is calculated by a method such as chain retrieval.
(4) The error value is calculated and the value of the information data at the error position is corrected to the result of an exclusive OR operation performed on the value of information data at the error position and the error value.
The construction of error correction unit 1150 is explained below in accordance with FIG. 4.
FIG. 4 shows the construction of conventional error correction unit 1150.
Error correction unit 1150 includes syndrome calculation circuit 1151, Euclidean calculation circuit 1152, chain calculation circuit 1153, and erroneous data correction circuit 1154.
Syndrome calculation circuit 1151 performs operation (1) in the above-mentioned process. Euclidean calculation circuit 1152 performs operation (2), chain calculation circuit 1153 performs operation (3), and erroneous data correction circuit 1154 performs their operation (4). These circuits synchronize their operations with each other and perform the operations in parallel. Consequently, these circuits perform serial processing in a pipelined architecture.
The bold lines in FIG. 4 show the flow of the data to and from first memory 1110.
Syndrome calculation circuit 1151 fetches the data stored in first memory 1110 to perform a calculation, and transfers the result of the calculation to Euclidean calculation circuit 1152. Euclidean calculation circuit 1152 transfers its calculation result to chain calculation circuit 1153. Chain calculation circuit 1153 transfers its calculation result to erroneous data correction circuit 1154. Erroneous data correction circuit 1154 calculates the value of the error included in the data, performs an exclusive OR operation on the error value and the value of the information data at the error position stored in first memory 1110, and overwrites the result of the exclusive OR operation over the value of the information data. Erroneous data correction circuit 1154 then updates the information data stored in first memory 1110.
FIG. 5 shows the parallel processing performed in conventional error correction unit 1150.
No. 1, or No. 2 in FIG. 5 shows a coded data sequence, for instance, one row of information data to which the parity data in C1 direction is added as mentioned above. Each of the data sequences is a block-coded "codeword", which is called a "received word" when received via a channel. The above-mentioned block coding is a coding performed on one set of data, for instance, one row of data, independently of the coding performed on other sets of data, which is to say, other rows of data. The channel mentioned above is the path, which includes pickup 1020 and the like, by which the data recorded on an optical disc is read and transferred to optical disc control unit 1100.
The lengths of the bold lines in FIG. 5 show the time taken to perform each task.
FIG. 5 shows that each circuit performs calculation on a different data sequence in each period of time, and that no two circuits perform calculation on the same data sequence in any one period of time. For instance, syndrome calculation circuit 1151 calculates data sequence No. 4 in time t4, and calculates data sequence No. 5 in time t5. Euclidean calculation circuit 1152 calculates data sequence No. 3, and chain calculation circuit 1153 calculates data sequence No. 2, and erroneous data correction circuit 1154 calculates data sequence No. 1, in time t4.
Each period of time, such as t1 or t2, is set at the longest processing time of the four circuits in order that the four circuits perform serial processing in a pipelined architecture.
More specifically, the time taken by the processing of each circuit is different as shown by the bold lines in FIG. 5, so that for serial processing in a pipeline architecture to be possible, appropriate wait times need to be set for the various circuits. Generally speaking, the time for the calculation performed in the Euclidean calculation circuit is longer than that in the syndrome calculation circuit, the chain calculation circuit, or the erroneous data correction circuit.
The optical disc reader, which has been explained above as an example of a conventional data input output device, has the problems described below.
Firstly, two memories that store the same data, for instance, the first memory and the third memory in optical disc control unit 1100, are include din the conventional data input-output device. This is because the data transmission rates for inputting data and outputting data are different. This is also because a structure where the same unit is in charge of the calculations of the input data and the high speed output of the data would require complicated memory access control. It is undesirable to inefficiently use a memory, such as the first memory in optical disc control unit 1100, in a data input-output device.
Secondly, the serial processing in a pipelined architecture performed by the four circuits in error correction unit 1150 generates the waiting time for all the circuits except the circuit requiring the longest processing time.
These days an increasing number of consumers are demanding electric appliances and information equipment that are more compact and have higher performance. Under the circumstances, solving the above-mentioned problems of ineffective memory and futile waiting time has direct and indirect effects on the realization of compactness and higher performance.